python2verilog.backend.verilog package

Submodules

python2verilog.backend.verilog.ast module

Verilog Abstract Syntax Tree Components

class Always(trigger: Expression, *args, body: list[Statement] | None = None, **kwargs)

Bases: Statement

always () begin

…

end

to_lines()

To Verilog

class AtNegedge(condition: Expression)

Bases: Expression

@(negedge <condition>)

class AtNegedgeStatement(condition: Expression, *args, **kwargs)

Bases: Statement

@(negedge <condition>);

class AtPosedge(condition: Expression)

Bases: Expression

@(posedge <condition>)

class AtPosedgeStatement(condition: Expression, *args, **kwargs)

Bases: Statement

@(posedge <condition>);

class BlockingSub(lvalue: Var, rvalue: Expression, *args, **kwargs)

Bases: Subsitution

<lvalue> = <rvalue>

class Case(expression: Expression, case_items: list[CaseItem], *args, **kwargs)

Bases: Statement

Verilog case statement with various cases case (<expression>)

<items[0]> … <items[n]>

endcase

to_lines()

To Verilog Lines

class CaseItem(condition: Expression, statements: list[Statement])

Bases: ImplementsToLines

Verilog case item, i.e. <condition>: begin

<statements>

end

to_lines()

To Verilog lines

class Declaration(name: str, *args, size: int = 32, reg: bool = False, signed: bool = False, **kwargs)

Bases: Statement

<reg or wire> <modifiers> <[size-1:0]> <name>;

to_lines()

To Verilog lines

class IfElse(condition: Expression, then_body: list[Statement], else_body: list[Statement] | None, *args, **kwargs)

Bases: Statement

Verilog if else

to_lines()

To Verilog

class Initial(*args, body: list[Statement] | None = None, **kwargs)

Bases: Statement

initial begin

…

end

to_lines()

To Verilog

class Instantiation(module_name: str, given_name: str, port_connections: dict[str, str], *args, **kwargs)

Bases: Statement

Instantiationo f Verilog module. <module-name> <given-name> (…);

to_lines()

To Verilog

class LocalParam(name: str, value: UInt, *args, **kwargs)

Bases: Statement

localparam <name> = <value>;

class Module(name: str, body: list[Statement] | None = None, localparams: dict[str, UInt] | None = None, header: Lines | None = None)

Bases: ImplementsToLines

module name(…); endmodule

to_lines()

To Verilog

class NonBlockingSubsitution(lvalue: Var, rvalue: Expression, *args, **kwargs)

Bases: Subsitution

<lvalue> <= <rvalue>

class PosedgeSyncAlways(clock: Expression, *args, **kwargs)

Bases: Always

always @(posedge <clock>) begin

<valid> = 0;

end

class Statement(literal: str = '', comment: str = '')

Bases: ImplementsToLines, GenericRepr

Represents a statement in verilog (i.e. a line or a block) If used directly, it is treated as a string literal

get_blocked_comment()

// <comment> … // <comment> Separated by newlines

get_inline_comment()

// <comment>

to_lines()

To Verilog

class Subsitution(lvalue: Var, rvalue: Expression, oper: str, *args, **kwargs)

Bases: Statement

Interface for <lvalue> <blocking or nonblocking> <rvalue>

to_lines()

Converts to Verilog

class TypeDef(name: str, values: list[str])

Bases: Statement

typedef enum {

<val0>, <val1>, …

} _state_t;

to_lines()

To Verilog

class While(*args, condition: Expression, body: list[Statement] | None = None, **kwargs)

Bases: Statement

Unsynthesizable While while (<condition>) begin

…

end

to_lines()

To Verilog

python2verilog.backend.verilog.codegen module

Verilog Codegen

class CodeGen(root: Node, context: Context, config: CodegenConfig | None = None)

Bases: object

Builds the Verilog ast from the context and IR

get_module()

Get Verilog module

get_module_lines()

Get Verilog module as Lines

get_module_str()

Get Verilog module as string

get_testbench(config: TestbenchConfig)

Creates testbench with multiple test cases

Each element of self.context.test_cases represents a single test case

Parameters:

random_ready – whether or not to have random ready signal in the while loop

get_testbench_lines(config: TestbenchConfig)

New Testbench as lines

get_testbench_str(config: TestbenchConfig)

New testbench as str

python2verilog.backend.verilog.config module

Configurations

class CodegenConfig(random_ready: bool = False, add_debug_comments: bool = <factory>)

Bases: TestbenchConfig

Configurations for code generator

add_debug_comments: bool

class TestbenchConfig(random_ready: bool = False)

Bases: object

Configurations for test bench code generator

random_ready: bool = False

python2verilog.backend.verilog.fsm module

Lowers IR Graph to FSM

class FsmBuilder(root: Node, context: Context, config: CodegenConfig | None = None)

Bases: object

Creates a FSM using a case block from a IR Graph

static create_quick_done(context: Context) → IfElse

if ready:

done = 1 state = idle

else:

state = done

do_edge(edge: Edge)

Processes a edge

do_vertex(vertex: Node)

Processes a node

get_case() → Case

Gets case statement/block

new_caseitem(root: Node)

Creates a new case item with the root’s unique id as identifier

python2verilog.backend.verilog.module module

Creates module from context and FSM

class Module(context: Context, root: Case)

Bases: Module

A module that implements the python2verilog module interface

static make_start_ifelse(root: Case, context: Context) → list[Statement]

if (_start) begin

…

end else begin

…

end

python2verilog.backend.verilog.testbench module

Creates testbench from context and FSM

class Testbench(context: Context, config: TestbenchConfig)

Bases: Module

Module contents

Verilog Backend